Integrated circuits (“ICs”) operate at high-frequencies. Byproducts of such high-frequency operation may include various forms of noise, including without limitation high-frequency voltage ripple (“Vr”) present in an on-die power supply voltage.
A stacked die assembly (“stacked die”) may include one or more IC die coupled to an interposer, which interposer is coupled to a package substrate. Such stacked die may be coupled to a printed circuit board (“PCB”). Such package substrate and PCB may have parasitic inductance (“L”), which in combination with changes in on-die current (“di/dt”), may promote voltage ripple. A first order approximation of voltage ripple (i.e., Vr˜L di/dt) may be used to understand that as frequency increases, namely as the term dt decreases, voltage ripple may increase. Such voltage ripple or ripple voltage may increase to unacceptable levels for some applications, which may adversely impact analog and/or digital circuits that are sensitive to voltage ripple on a power supply voltage or other supply voltage.
Accordingly, it would be desirable and useful to reduce supply voltage noise.